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CoreFFT Fast Fourier Transform
sequence of stages with the final result obtained at the
last computational stage. As soon as a final output vector
is ready, the FFT module puts out an N-word frame of FFT
results.
An FFT-based system ( Figure 1 ) consists of the following:
? A host presenting data to the FFT module to be
processed
? The FFT module
A negative nreset signal resets the FFT module. After
reset (input nreset taken HIGH), the module enters an
initialization state where internal RAM-based lookup
tables (LUTs) are initialized. Once initialization is
complete, the CoreFFT module automatically switches to
a ready state, prepared to receive data samples to be
processed. The module input start can be used to bring
the module to the ready state at any time after
initialization.
?
A host accepting processed data
Note: The CoreFFT module will discard data collected in
Note: Signals shown in parentheses are optional. The
host may use/generate these optional signals if required
its input and output buffers when start is taken HIGH by
the host.
by the application.
(Keep
b -Bit
Imaginary
Data
d_im
FFT
load
Supplying Data)
HOST
Source of
Data to Be
FFTed
b -Bit
Real Data
Input Data
Validity Bit
d_re
d_valid
y_im
y_re
b -Bit
Imaginary
Data
b -Bit
Real Data
(Start FFT)
start
nreset
clk
read_y
y_valid
y_rdy
pong
FFT Result
Validity Bit
(FFT Results
are available)
(1-Bit Data ID)
HOST
Receiver of
FFTed Data
(output of another
FFTed sample)
Global
Reset
Master Clock
Figure 1 ? FFT Module System Block Diagram
The data-source host supplies the FFT engine with the
data to be transformed. Every complex input data
sample (i.e., a pair of b -bit imaginary and real words) is
accompanied with a validity bit. Upon receiving the
validity bit, the module assumes a valid complex data
sample is present on both b -bit input data busses.
Once the input data buffer is full, CoreFFT automatically
starts processing data stored in the buffer. At this time,
the host source should stop supplying the data to
CoreFFT, thus ending a current burst of input data. The
data-source host can do so either by counting the
number of input samples transferred or by monitoring
the state of the module signal, load . The CoreFFT
module drives load LOW once N samples (N is a
transform size) of the current burst are received into the
input buffer. As soon as the dual input buffer is ready for
the next data burst, load is asserted again. The module is
then ready to receive the next data burst to be
processed.
The data-source host can supply data at a maximum of
every clock cycle, or it may skip an arbitrary number of
"empty" clock periods. The host signals to the module
that no data is being transferred for a given clock cycle
by taking the validity bit d_valid LOW.
2
v4.0
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